Technical Field
The present disclosure relates to a method and structure for forming strained transistors.
Description of the Related Art
Scaling of transistor size has served to improve switching speed (the maximum speed at which a transistor can be switched off or on), conduction properties, and circuit density. However as CMOS technology has reached the 32 nm and 16 nm nodes, scaling has become more difficult and new means for improving device function have been sought.
One means for improving transistor properties is to introduce strain in the channel of the transistor. This has been done by carefully forming strain inducing layers of materials above the channel region of the transistor. The strain inducing layers induce either a tensile or compressive strain on the channel region of the transistor, according to the type of the transistor, and in so doing improve carrier mobility in the channel region. The improved carrier mobility enhances current conduction in the channel region, which in turn allows for lower power dissipation and enhanced transconductance. The enhanced transconductance means that a larger current can be induced in the channel with a smaller gate to source voltage, allowing for lower supply voltages to be used on chip. The lower supply voltages allow for further reduction of power dissipation
It is known in the art that a transistor subjected to different types of stress increases the mobility of the charge carriers in the channel region. For example, creating a tensile stress in the channel region increases the mobility of electrons and, depending on the magnitude of the stress, increases in mobility of up to 20% may be obtained. This, in turn, directly translates into an increase in conductivity and faster speed. Similarly, compressive stress in the channel region may increase the mobility of holes, thereby providing enhanced performance of those transistors which conduct based on the mobility of holes.
Consequently, it is has been proposed to introduce a compressive stress into the channel region of N-type transistors and a tensile stress into the channel region of P-type transistors. A number of structures have been proposed in the prior art to induce stress in these respective channel regions.
A common MOS transistor includes source, drain, and channel regions formed in a mono crystalline semiconductor substrate. A gate electrode is positioned over the channel region. Sidewall spacers are formed adjacent the gate electrode.
Strain is induced in the channel region of the transistor by depositing a dielectric layer over the gate electrode, the sidewall spacers, and the source and drain regions. Silicon nitride is commonly used for a strain inducing dielectric layer 56, but other strain inducing layers are also used. The Si3N4 strain inducing layer may be deposited by means of a low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or other suitable methods.
A silicon nitride layer 56 can have compressive or tensile strain characteristics depending on the conditions during formation of the silicon nitride. Silicon nitride can be formed by PECVD in a chamber in the presence of silane (SiH4), N2, and ammonia (NH3). By varying the silane flow rate, the ammonia flow rate, the N2 flow rate, the pressure, temperature (both before and after deposition), and the low and high frequency power outputs in the deposition chamber, a silicon nitride layer can be made to have varying levels of compressive or tensile strain.
A structure of this type is described and shown in detail in U.S. Patent Application Publication No. 2005/0263825 to Frohberg et al., (the '825 application) which is incorporated herein by reference.
Another method for increasing carrier mobility in an NMOS device is to implant carbon and phosphorus into the silicon source and drain regions of the transistor. The carbon and phosphorus are implanted into the silicon with an acceleration energy of 15 KeV. If the implantation is performed at room temperature, many residual crystal defects occur in the silicon substrate. Such crystal defects include dislocations, stacking faults, and arrange defects. These defects can be partially avoided if the implantation is performed at very cold temperatures, for example −60°. However, implanting at this low temperature is also very expensive and time-consuming.